As is known, at present, amplifiers of the above type perform a standby function wherein the amplifier is supplied with power but the current paths are interrupted as much as possible to minimize (theoretically eliminate) absorption; in that condition, any signals at the input are not transferred to the output of the amplifier.
For clarity, a typical existing audio amplifier of the above type is described with reference to the block diagram in FIG. 1.
The FIG. 1 amplifier, indicated by reference numeral 1, is substantially composed of three cascade stages: an input stage 2; a voltage amplifying stage 3; and an output stage 4 operating as a current amplifier.
Input stage 2 comprises a transconductance amplifier Gm1, i.e., an amplifier with a voltage input and a current output, and presents a noninverting input connected to an input terminal 5 that is supplied with an input signal V.sub.IN to be amplified. An input resistor 6 is also provided between terminal 5 and ground. Input stage 2 also presents an inverting input connected to a feedback line 7, and is connected to a first supply line 10 (at voltage V.sub.CC) via a first switch 11 controlled by a logic signal S1.
Voltage amplifying stage 3 is exemplified by a transistor 14, here a bipolar NPN type, with the base terminal connected to the output of input stage 2 at node 12, the emitter terminal connected to a second supply terminal 15 at voltage -V.sub.CC, and the collector terminal connected at node 13 to a current source 16, which is also connected to first supply line 10 via a second switch 17, which is also controlled by signal S1. A compensating capacitor 18 is provided between the collector and base terminals of transistor 14.
Output stage 4 substantially operates as a buffer, and presents an input connected to the collector terminal of transistor 14 at node 13, and an output 19 defining the output of amplifier 1 and connected directly to one terminal of a load 20, represented here by a resistor that is grounded at its other terminal. The voltage across load 20 is V.sub.0. Output stage 4 is connected to first supply line 10 via a third switch 21 controlled by the same logic signal S1 as switches 11 and 17, so that, when switch 21 is open, output stage 4 is turned off and disconnects the load from the rest of amplifier 1.
Feedback line 7 comprises a block 22 having a transfer function .beta. and connected between output 19 of amplifier 1 and the inverting input of input stage 2.
When the FIG. 1 amplifier is in standby mode, logic signal S1 assumes a level (indicated "logic 0" in FIG. 2) corresponding to the open condition of switches 11, 17 and 21, so that stages 2, 3 and 4 are disconnected from the positive supply; voltage V.sub.1 with respect to ground at the base terminal and voltage V.sub.2 at the collector terminal of transistor 14 are equal V.sub.1 =V.sub.2 =-V.sub.CC, i.e., equal the negative supply voltage of line 15; capacitor 18 is discharged; and output voltage V.sub.0 is zero (FIG. 2).
When amplifier 1 is turned on, logic signal S1 switches to a logic state ("1" in FIG. 2) such as to close switches 11, 17, 21, so that stages 2-4 are turned on, and amplifier 1 evolves towards the balanced bias condition (steady state). More specifically, in the transient interval, capacitor 18 is charged from 0 V to V.sub.CC so that voltage V.sub.2 is brought from -V.sub.CC to 0 V; and voltage V.sub.0 at the load follows voltage V.sub.2 at the input of the final stage, so that, when switch 21 is closed and final stage 4 turned on, it presents a negative peak of approximately -V.sub.CC followed by an increase up to the steady-state value of approximately 0 volts, as shown in FIG. 2.
To eliminate the negative peak, nodes 12 and 13 may be appropriately biased by connecting them to voltage sources each of a predetermined value, where these voltage sources are only active in the transient interval from standby mode. Such a solution, however, is difficult to implement in that, for it to function properly, the values of the voltages supplied depend upon the specific circuit involved and are highly unpredictable, especially as regards voltage V.sub.1 at node 12.
Neither is it possible to simply keep final stage 4 off during the transient interval, as this would not guarantee circuit 1 reaching the steady-state condition. If in fact, stage 4 were kept off during the transient interval, input stage 2 would be unaware of developments in the circuit via feedback branch 7 by virtue of node 13 being disconnected from node 19 to which input stage 2 is connected.